On May 25, a speech and a paper by He Tingbo, President of Huawei's semiconductor business unit, ignited China's chip industry. In this public appearance, He condensed Huawei's six-year chipmaking journey into a single paper and a theory.
Amid years of advanced process technology restrictions, Huawei's semiconductor team has mass-produced 361 chip models. Through these chips, they have confirmed a conclusion: blindly increasing transistor density and chip performance through "geometric scaling" (shrinking transistor size) has approached physical and cost limits. Reducing the time constant (τ) and adopting "time scaling" is emerging as a new chip design path to circumvent extreme process dependency.
This is the Tau (τ) Scaling Law proposed by Huawei, intended to replace Moore's Law in the chip design domain.
Based on this, He predicts that by 2031, the transistor density of high-end chips following this roadmap will reach a level equivalent to a 1.4nm process. Notably, even TSMC and Intel's 1.4nm process technologies are not expected to enter mass production until 2029.
On April 19, 1965, the US journal Electronics published an article titled "Cramming More Components onto Integrated Circuits (IC)" by Gordon Moore, then director of Fairchild Semiconductor's research and development laboratory. In this brief paper, Moore made his observation: Since the advent of the integrated circuit in 1959, the number of components on an IC had roughly doubled every year, and he predicted this trend would continue for at least the next decade.
This observation later became famous as Moore's Law, revised by Moore himself in 1975 to "doubling every two years."
For a long time thereafter, Moore's Law served as the "industry covenant" for the global semiconductor industry, driving the greatest technological explosion in human history from personal computers to smartphones, from the internet to artificial intelligence, where computing power grew exponentially while costs continuously declined.
In 1974, IBM scientists Robert Dennard and colleagues published a paper proposing Dennard scaling. This theory states that as transistors shrink proportionally, voltage and current also scale down, maintaining a constant electric field and thus keeping power density unchanged.
This theory aligned perfectly with the then-dominant Moore's Law, because while transistor counts grew exponentially, performance-per-watt and performance-per-cost improved simultaneously.
However, this "covenant" began to crack in the early 2000s.
Around 2005, Dennard scaling first broke down. As feature sizes entered below 90nm, the thinning of traditional silicon dioxide gate insulators led to a sharp rise in quantum tunneling leakage current. Voltage could no longer scale down proportionally, and the "dark silicon" phenomenon also emerged—more and more transistors on a chip could not operate simultaneously due to power constraints.
Clock frequency stagnated from that point onward, and multi-core architectures became mainstream.
This is why, when discussing smartphone and laptop performance, the number of CPU cores has been increasingly mentioned and has become an important parameter for measuring CPU performance.
Nevertheless, geometric scaling (pure dimensional shrinkage) did not collapse overnight. It went through multiple cycles of doubt and reversal, behind which companies like Intel, through continuous upgrades such as EUV lithography and FinFET technology, pushed chip process nodes further to 7nm, 5nm, and even more advanced processes.
Just this year, the launch of the 18A (1.8nm) process gave Intel, which had been surpassed by Nvidia and AMD, a much-needed boost.
But after entering the 7nm node, subtle changes began to occur:
The returns from chip process scaling began to diminish sharply. Velocity saturation turned the improvement in delay from channel length from quadratic to linear (slowing down), while cost per transistor stopped declining and even rose at some advanced nodes. These phenomena led, after 2010, multiple industry leaders to openly acknowledge the slowing of Moore's Law.
In fact, as early as 2003, Moore himself predicted that no exponential growth could continue forever. By around 2020, the purely geometric "industry covenant" had in fact become unsustainable.
The end of Moore's Law is not a sudden death but a gradual decline. It marks the semiconductor industry's transition from the "easy era" to the "difficult era":
Under the triple pressures of physical, economic, and application limits, the traditional model can no longer be sustained. The entire computing stack urgently needs new optimization targets.
On October 10, 2018, at the Huawei Connect conference in Shanghai, Huawei's rotating chairman Xu Zhijun officially released Huawei's full-stack, all-scenario AI strategy. During this event, the previously speculated AI project also made its formal debut.
Alongside the project came Huawei's first self-developed AI chips for the AI domain based on its Da Vinci architecture—Ascend 910 and Ascend 310. According to Huawei's official data at the time, the Ascend 910 delivered 256 TFLOPS of FP16 computing power on a single chip, achieving industry-leading compute density.
This was a major milestone in Huawei's "chip-making" strategy, but greater challenges followed.
In May 2019, the US added Huawei to the Entity List, and in 2020, further tightened export controls. Huawei was thereby cut off from global advanced process supply, prompting its semiconductor team to embark on a six-year march.
Under extreme pressure, between 2020 and 2026, Huawei's semiconductor team designed and mass-produced 381 chips, covering mobile, AI, automotive, infrastructure, and other fields.
Constrained by limited access to advanced lithography, they shifted their optimization target from "geometric scaling" to "time scaling" (τ scaling), systematically reducing the single characteristic time constant τ, from picosecond-level transistors to second-level system workloads.
On May 25, 2026, at the IEEE ISCAS conference, He formally proposed the Tau (τ) Scaling Law, advocating time rather than transistor area as the primary optimization metric.
Tau (τ) Scaling Law thus became, after Dennard scaling, another shared optimization target across the entire computing stack.
Furthermore, based on this law, Huawei set an advanced chip development goal for itself: by 2031, following this roadmap, the transistor density of high-end chips would reach a level equivalent to a 1.4nm process.
Although Huawei's chipmaking efforts were no secret in the industry, the proposal and public disclosure of the Tau (τ) Scaling Law still caused a huge stir. After being choked by advanced process restrictions, the development of China's domestic chips has drawn global attention.
In an era of global industrial division of labor, without the synergy of global supply chains, can China produce a chip giant capable of competing with Nvidia, Intel, and AMD? This is one of the hottest questions in the global chip industry.
In fact, after the new AI paradigm of large language models ignited demand for computing power, the global computing industry has been undergoing a reshaping. Global tech giants have begun designing their own chips, and the chip industry chain is searching for new paradigms in the post-Moore's Law era.
Meanwhile, China's chip industry has quietly completed a fundamental bottom-up transformation. In design, manufacturing, packaging, and testing, China is gradually filling its gaps, and several leading companies are moving from behind the scenes to the forefront.
A Reuters report from late April noted that after news broke of DeepSeek V4 migrating to Huawei's Ascend 950PR, domestic internet giants including ByteDance, Alibaba, and Tencent began contacting Huawei to discuss chip orders.
On the path pointed out by Tau (τ) Scaling Law for the post-Moore era, the industry's competitive focus is shifting from process scaling to architectural innovation, system optimization, 3D integration, and algorithm-hardware co-design.
Under such a new paradigm, can China cultivate a global chip giant?
(With input from 36kr)
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